Astrit Ademaj
- Dr.Sc.
- Full Time Staff
Publications
- Combination of clock-state and clock-rate correction in fault-tolerant distributed systems
- A maintenance-oriented fault model for the DECOS integrated diagnostic architecture
- Software implementation of a time-triggered ethernet controller
- Application-Level Diagnostic and Membership Protocols for Generic Time-Triggered Systems
- Segmentation of standard ethernet messages in the time-triggered ethernet
- A Tunable Add-On Diagnostic Protocol for Time-Triggered Systems
- Fault tolerance evaluation using two software based fault injection methods
- Hardware Implementation of the Time-Triggered Ethernet Controller
- Time-Triggered Ethernet and IEEE 1588 Clock Synchronization
- Integration of internal and external clock synchronization by the combination of clock-state and clock-rate correction in fault-tolerant distributed systems
- Slightly-off-specification failures in the time-triggered architecture
- A time-triggered ethernet (TTE) switch
- Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology
- The time-triggered Ethernet (TTE) design